1. Field of the Invention
The present invention relates to the reduction of current consumption in redundancy judging unit of a semiconductor memory device, and more particularly to the reduction of current consumption when a static-type redundancy judging unit is used.
2. Description of the Related Art
Conventionally, with respect to a semiconductor memory device, the demand for finer circuit design and large capacity have been accelerated. However, the occurrence probability of defects on layout derived from particles or the like has been increased along with the finer circuit design, while the occurrence probability of defects has been also increased derived from the increase of die size along with the increase of capacity whereby, as a whole, there has been observed a tendency that the number of defects in memory cells has been increasing. Accordingly, there has been observed a tendency that the number of defective memory cells to be relieved is increasing due to the failure of characteristics derived from defects. Along with the increase of the number of defective memory cells, the number of redundancy judging circuits for replacing the defective memory cells with auxiliary memory cells is increased whereby the current consumption caused by the redundancy judging operation has been increasing. Since the judging operation is performed each time an access operation to the memory cells is performed, the reduction of current consumption caused by the redundancy judging operation has been demanded.
Further, in the technical field of portable equipment which has been sharply developed recently, along with the increase of functions incorporated into the portable equipment, a semiconductor memory device having a large capacity has been demanded and hence, a dynamic random access memory (hereinafter referred to as xe2x80x9cDRAMxe2x80x9d) has been adopted in view of the high integration density of a memory cell structure. The DRAM which is mounted in the portable equipment has been subjected to the refreshing operation such as the self-refreshing operation or the like even in the non-access period during standby time. Here, with respect to the current consumption at the time of refreshing operation, except for the selection of memory cell and the operation of a memory cell core section such as the amplification of cell data, the judging operation performed by the redundancy judging circuit occupies a large portion of the operation of peripheral circuits. Accordingly, with respect to the portable equipment such as a portable telephone or a digital camera which is held in the standby state for a long period, to enhance the continuous service time characteristics at the time of driving a battery, it is dispensable to reduce the current consumption at the standby state. Accordingly, the reduction of the current consumption of the redundancy judging operation at the time of refreshing operation in the semiconductor memory device such as DRAM or the like is extremely important.
To cope with the demand for the reduction of current consumption of the above-mentioned redundancy judging operation, in the first prior art shown in FIG. 9 corresponding to Japanese Laid-open Patent Publication No. 5-252998, a power-on signal PON is set in low level when the power is turned on. When a fuse 603 is cut, an output of a latch circuit 604 is set in high level, p-channel transistors 608, 609 and 610 are turned on so that the redundancy judging function realized by a redundancy address judging circuit 300 becomes effective. When the fuse 603 is not cut, the output of the latch circuit 604 is set in low level and the three p-channel transistors 608, 609 and 610 are turned off so that the redundancy address judging circuit 300 becomes inoperative. When there exists no defective memory cell or an auxiliary memory cell is not used, the current consumption is reduced by stopping the operation of the redundancy address judging circuit 300.
Further, as the second prior art, comparing/selecting unit disclosed in Japanese Laid-open Patent Publication No. 3-307898 is shown in FIG. 10. Storing of defective cell addresses to fuse elements F110 to Fn20 of a comparing/selection circuit 100 is performed by cutting the fuse elements which correspond to a bit xe2x80x9c1xe2x80x9d among bits A1 to An or complements thereof A1b to Anb of corresponding input address codes. At a point of time that an input address code which coincides with the address of the defective cell is supplied to a comparing/selecting circuit 100, the bit xe2x80x9c1xe2x80x9d is received by a gate electrode and the fuse elements which are connected to transistors Q110 to Qn20 to be turned on are all cut so that a driving voltage from a driving pulse supply circuit 120 holds the value as it is at an output node N100. When the input address code does not coincide with the address of the defective cell, since there exists at least one transistor which is connected to the fuse element which is not cut and receives the bit xe2x80x9c1xe2x80x9d at the gate electrode, the potential of the output node N100 is lowered to a ground potential. The supply of the driving voltage to the output node N100 is performed through the fuse element F100 and the transistor Q100 of a driving pulse supply circuit 120. However, with respect to the surplus comparing/selecting circuit 100, the fuse element F100 is cut so as to stop the generation of an electric current which flows into the output node N100 whereby the consumption of power can be saved.
Further, in the portable equipment, it is necessary to reduce the current consumption during standby time as much as possible. Accordingly, with respect to a DRAM served for operation, there have been proposed several methods for reducing the current consumption generated by the refreshing operation which is a major factor causing current consumption during standby time as much as possible. Relieving of defective memory cells using a so-called refreshing redundancy is one of such measures.
In FIG. 11 and FIG. 12, a concept of refreshing redundancy is shown. In FIG. 11, a memory cell core section 1000 of a semiconductor memory device is shown schematically. The memory cell core section 1000 is constituted of a memory cell array section 1100 and an auxiliary memory cell array section 1200. In the memory cell array section 1100, memory cells (MC0 to MC2 and the like) are properly arranged at intersections of word lines WL0 to WLn and bit lines BL0 to BLn. In the auxiliary memory cell array section 1200, redundancy memory cells (SMC0 and the like) are properly arranged at intersections of redundancy word lines SWL0 to SWLm and redundancy bit lines SBL0 to SBLn.
Further, FIG. 12 schematically shows the characteristic distribution of memory cells using a data holding time tREF of the memory cells (MC0 to MC2 and the like) as a parameter. Using a data holding time t1 (tREF=t1) as a lower limit value of data holding characteristics, the memory cells (MC0 and the like) which have the data holding time tREF longer than the lower limit value constitute normal memory cells. The memory cells (MC2 and the like) having characteristics in which the data holding time tREF is below the lower limit value t1 and reaches a lowermost limit value t0 (lower limit value in a usual DRAM) constitute memory cells having defective tREF characteristics. The memory cells (MC1 and the like) whose data holding time tREF is equal to or below the lowermost limit value t0 include, as shown in FIG. 11, the memory cells which are not accessible due to a layout defect such as the disconnection of the word line WL1 and these memory cells constitute access disabled memory cells (MC1 and the like).
In the memory cells, since a charge stored in a memory cell capacitor is lowered below the reference voltage in the data holding time tREF and the data is dissipated, it is necessary to set a period of refreshing within the data holding time tREF. Accordingly, the memory cells (MC1, MC2 and the like) whose data holding characteristics are equal to or below the lower limit value t0 of the data holding time tREF are treated as defective cells. Recently, DRAMs have been used in the portable equipments and the demand for the reduction of current consumption during standby time has been sharply increasing. In view of such circumstances, because of the necessity to reduce the current consumption at the time of performing the refreshing operation which constitutes a major factor in the current consumption during standby time, the longer refreshing period has been requested compared to conventional art, and hence, a strict specification is set such that the lower limit value of the data holding time tREF is set to a lower limit value t1 compared to a lowermost limit value t0 for usual DRAM use.
Accordingly, the memory cells (MC2 and the like) which have been judged as normal cells in the usual DRAM use are judged as defective cells thus leading to the reduction of the yield rate. The refreshing redundancy is a method which has been provided for preventing this reduction of the yield rate. The usual relieving of defects of memory cells using the auxiliary memory cells, aims at relieving access disabled cells (MC1 and the like), wherein the word line WL1 is can be changed to the redundant word line SWL0 shown in FIG. 11. The refreshing redundancy also aims at, in addition to the above, changing cells having defective data holding characteristics (MC2 and the like) to redundant cells. On the memory cell array section 1100, the memory cells (MC2 and the like) are distributed at arbitrary positions and respective word lines WL2, WLk, WLn can be changed to the redundant word lines SWL1, SW2, SWLm. The refreshing redundancy contributes to the enhancement of the yield rate of DRAMs whose refreshing period is long and the current consumption during standby time is reduced.
In adopting the refreshing redundancy, in addition to the auxiliary memory cells for relieving the access disabled cells (MC1 and the like), the cells having defective data holding characteristics (MC2 and the like) which are widely distributed within the memory cell array section 1100 are also relieved and hence, a larger number of redundancy judging circuits are necessary than usual DRAMs. The reduction of the current consumption of the redundancy judging circuits has been requested also from this aspect.
In the prior art, by performing the redundancy judging operation by the redundancy judging circuits only when the auxiliary memory cells are used so as to reduce the current consumption in the redundancy judging circuits when the relieving by the auxiliary memory cells is not performed. However, this prior art has a drawback that the current consumption reduction effect is insufficient. Particularly, when the DRAM is used in the application such as the portable equipment in which it is necessary to reduce the standby current to an extreme, it is necessary to drastically reduce the current consumption by the redundancy judging circuits at the time of refreshing operation. However, the prior art is insufficient to cope with such a situation and there arises several problems. To be more specific, following problems exist.
In Japanese Laid-open Patent Publication No. 3-252998, by preventing the fuse 603 from being cut when the defective memory cell is not present and the auxiliary memory cell is not used, it is possible to reduce the current consumption by stopping the operation of the redundancy address judging circuit 300. However, the fuse 603 merely indicates the judgment whether the semiconductor memory device uses the auxiliary memory cells or not so that when the auxiliary memory cell is used, the fuse 603 is cut and the redundancy address judging circuit 300 is operated. Accordingly, when the auxiliary memory cells are present in a plural number and any one of them is used, all redundancy address judging circuits 300 are operated so that the redundancy address judging circuit 300 which is unused and is not necessary to operate is also operated. Accordingly, there arises a problem that the current is wasted due to undesired circuit operation so that the reduction of the current consumption can not be achieved sufficiently.
Further, the stopping of operation of the redundancy address judging circuit 300 is performed by interrupting a propagation path of a start signal transmitted from a row start trigger circuit. Apart from the above, a row address which constitutes an object of the redundancy judgment is inputted into the redundancy address judging circuit 300. This row address is inputted to the redundancy address judging circuit 300 irrespective of the presence or the absence of the start signal from the row start trigger circuit and hence, there is a possibility that corresponding to the transition of the row address, an input stage circuit of the redundancy address judging circuit 300 is driven. When the input stage circuit is operated irrespective of the presence or the absence of the operation of the redundancy address judging circuit 300, the current is wasted due to the undesired circuit operation so that there arises a problem that the reduction of the current consumption can not be achieved sufficiently.
In Japanese Laid-open Patent Publication No. 5-307898, with respect to the surplus comparing/selection circuit 100, it is possible to save the power consumption by cutting the fuse element F100 thus stopping the inflow of current into the output node N100. However, although the charge/discharge current to the output node N100 can be reduced by interrupting a supply path of a driving voltage to the output node N100, the charge/discharge current of the gate electrodes of transistors Q110 to Qn20 to which the output node N100 discharges cannot be reduced thus also giving rise to a problem. Particularly, it is necessary to input two complementary signals for every address bit to the gate electrodes of the transistors Q110 to Qn20. Further, also considering the circumstance that the number of address bits has been increased along with the progress of large capacity of the recent semiconductor memory device, the number of transistors Q110 to Qn20 has been increasing. Accordingly, the number of drain terminals of the transistors Q110 to Qn20 which are connected to an output node N100 is increased so that a junction capacitance added to the output node N100 is increased. Further, since this load capacitance has to be discharged within a predetermined time by at least one transistor, the transistors Q110 to Qn20 are required to have the sufficient driving ability whereby the size of the transistor is increased inevitably. From the above, the junction capacitance applied to the output node N100 is increased. Still further, the gate capacitance is also increased and this causes a problem that the gate charge/discharge current at the time of driving the transistors Q110 to Qn20 is increased thus giving rise to a problem.
Further, the comparing/selecting unit disclosed in Japanese Laid-Open Patent Publication No. 5-307898 pre-charges the output node N100 by preliminarily supplying a driving voltage to the output node N100. Then, when the input address code does not coincide with the stored defective cell address by cutting of the fuse element F110 to Fn20, the driving voltage of the output node N100 is discharged. The number of discharge paths of the output node N100 varies corresponding to the number of uncut fuse elements. That is, the number of discharge paths of the output node N100 varies from one path to the number of paths which correspond to the number of bits which constitute all input address codes. Accordingly, depending on the number of discharge paths, the discharge time of the output node N100 differs so that there arises irregularities with respect to the redundancy judging time. That is, the pre-charge state indicates the redundancy state and it is necessary to perform the dynamic operation in which the result of judgment is determined based on bred at a suitable timing after the lapse of discharge time through the discharge paths. There is no other way but to make this suitable timing match the discharge time at one path which constitutes the most delayed condition. Further, a predetermined timing tolerance must be added by taking irregularities of the semiconductor memory devices into consideration. These operations necessitate an undesired time before performing the redundancy judgment thus giving rise to a problem from a viewpoint of rapid operation. Accordingly, there has been desired the low current consumption at the redundancy judging circuit based on the static logic operation which can be operated with fixed times and can perform the redundancy judgment at the shortest timing.
Further, the reduction of power consumption at the time of refreshing operation is performed by the refreshing redundancy. However, to realize the refreshing redundancy, a larger number of auxiliary memory cells and a larger number of redundancy judging circuits become necessary. Further, it is a rare case that all of these auxiliary memory cells and redundancy judging circuits are used. Accordingly, only the redundancy judging circuits are operated while a large number of auxiliary memory cells remain unused so that there arises a problem that the undesired current consumption generated by the operation of these circuits is increased.
For example, in a synchronous type DRAM (hereinafter referred to as xe2x80x9cSDRAMxe2x80x9d) of 128 megabits, 256 units of auxiliary memory cells are present. Here, usually, the memory cell array section 1100 is controlled such that the section 1100 is divided into a plurality of memory cell blocks, wherein 256 units of auxiliary memory cells and the redundancy judging circuits are also arranged in a distributed manner for every memory cell block. Accordingly, the judgment of redundancy is performed with respect to respective memory cell blocks. On the other hand, the cells having defective characteristics (MC2 and the like) and the defective cells (MC1 and the like) are distributed irrelevant to the respective memory cell blocks. Accordingly, in performing the usual relieving of defective memory cells using the auxiliary memory cells, it is a rare case that all auxiliary memory cells are used. That is, the average use rate at an initial stage of the manufacturing process installation is, for example, approximately 50%. This implies that 128 units of redundancy judging circuits perform the undesired circuit operations thus giving rise to a problem that a large amount of current is wasted.
Further, along with the enhancement of the yield rate which is brought about by the progress of optimization of the manufacturing process, the use rate of the auxiliary memory cells is lowered thus giving rise to a problem that the increase of current consumption caused by the undesired circuit operation of the redundancy judging circuits is further accelerated.
The present invention has been made to solve the above-mentioned problems of the prior arts and it is an object of the present invention to provide a semiconductor memory device and a redundancy judging method which can reduce current consumption at the time of performing a static-type redundancy judging operation.
To achieve the above-mentioned object, according to one aspect of the present invention, there is provided a semiconductor memory device including at least one redundancy judging circuit, the redundancy judging circuit comprising: a redundancy setting section in which the presence or the absence of substitute to auxiliary memory cells is set, a plurality of comparing sections which compare inputted address information and redundancy address information to be substituted to the auxiliary memory cells for every bit based on an EXCLUSIVE-OR control which is constituted of a combinational logic circuit, a logic composing section which performs a logic operation of output signals from the comparing sections by combinational logic circuits and judges the accordance/discordance of the address information and the redundancy address information, and a logic fixing section which fixes at least one of output signals from the comparing sections to a predetermined logic level, wherein based on a non-redundancy setting signal from the redundancy setting section which indicates absence of substitute setting, the comparing sections are inactivated so that the comparing operation is stopped and the logic fixing section is activated.
In a redundancy judging method of a semiconductor memory device according to one aspect of the present invention, in case presence of substitute to auxiliary memory cells is set with respect to memory cells of a predetermined address, inputted address information and redundancy address information to be changed to the auxiliary memory cells are compared to each other for every bit based on an EXCLUSIVE-OR control which is constituted of a combinational logic, and comparison results obtained by the comparison operation are subjected to a logic operation based on combinational logic and the accordance/discordance of the address information and the redundancy address information is judged thus performing the redundancy judgment whether the change to the auxiliary memory cells is to be executed or not, and in case absence of substitute is set, the comparison operation is stopped and at least one of the comparison results is set to a predetermined value so that the redundancy judging result of absence of substitute to the auxiliary memory cells is obtained.
Here, the non-redundancy setting signal is a signal from the redundancy setting section and is a signal which is activated when the memory cells of predetermined addresses are not substituted to the auxiliary memory cells. The signal level in the activated state may be constituted of either a positive logic as a high logic level signal or a negative logic as a low logic level signal.
Accordingly, with respect to the redundancy judging unit such as the redundancy judging circuit or the redundancy judging method in which the redundancy judgment which discriminates the accordance of the address information and the redundancy address information is performed such that the address information and the redundancy address information are subjected to the comparing operation for every bit by performing the EXCLUSIVE-OR control using the combinational logic circuit or other combinational logic and, thereafter, the comparison results are subjected to the logic operation using the combinational logic circuit or other combinational logic whereby the redundancy judgment can be performed in a static manner, when there is absence of substitution to the auxiliary memory cells due to the non-redundancy setting signal or the like, the comparing units such as comparing sections or the comparing processes for each redundancy judging unit is inactivated individually so that the comparing operation is stopped at an initial stage of the redundancy judging operation.
Accordingly, the operations of the comparing units such as comparing sections or the comparing processes and the logic composing section at subsequent stage or the logic composing unit such as the judging process of accordance/discordance are stopped for each redundancy judging unit so that the undesired current consumption can be reduced.
Simultaneously, in the redundancy judging unit whose operation is stopped, at least one comparing result thereof is fixed to a predetermined value such as a predetermined logic level value and hence, the judging result indicating the discordance is outputted from this redundancy judging unit. Here, to perform the fixing of the comparing result to the predetermined logic level, it may be sufficient to provide at least one logic fixing unit such as a logic fixing section or a setting process. Even when the operation of the comparing unit is stopped, due to the necessity of the minimum logic fixing unit, the redundancy judgment indicating the discordance can be obtained so that the current consumption caused by the operation of the logic fixing unit can be reduced to the necessity of the minimum amount.
In a semiconductor memory device in which a plurality of auxiliary memory cells which are individually subjected to the substitute control for respective different redundancy judging unit are present, only redundancy judging unit which is subjected to the substitute setting can be operated so that the current consumption caused by the redundancy judging operation can be reduced to the necessity of the minimum amount.
Since individual comparing unit is also constituted of combinational logic circuit or the like, different from the dynamic-type constitution of the prior art, the input load of terminals to which respective bits of address information are inputted is small. The driving current for the input load caused along with the transition of the address information is also small whereby the current consumption reduction effect which is brought about by limiting the redundancy judging unit to be operated can be enhanced.
In the DRAM or the like which is used in the portable equipment, it is possible to reduce the current consumption caused by the redundancy judging unit during the refreshing operation for reducing the standby current to a limit and hence, the continuous use time characteristics at the time of battery driving can be enhanced.
When the semiconductor memory device is provided with the refreshing redundancy function, the semiconductor memory device is provided with a larger number of redundancy judging units compared to the usual DRAM or the like. In this case also, the operation of the undesired redundancy judging units can be stopped and hence, in addition to the reduction of the current consumption caused at the time of performing the refreshing operation using the refreshing redundancy function, it is also possible to reduce the current consumption caused by the redundancy judgment. The current consumption during standby time can be further reduced so that the continuous use time characteristics at the time of battery driving can be further enhanced.
Further, along with the lowering of the use rate of the auxiliary memory cells caused by the progress of optimization of the manufacturing process, the frequency of redundancy judgment is reduced so that the number of the undesired redundancy judging units are increased. Since the operations of these redundancy judging units can be individually stopped, it is possible to effectively reduce the current consumption of the semiconductor memory device in response to the use rate of the auxiliary memory cells.
Furthermore, according to another aspect of the present invention, there is provided a semiconductor memory device including at least one redundancy judging circuit, the redundancy judging circuit comprising: a redundancy setting section in which the presence or the absence of substitute to auxiliary memory cells is set, a plurality of comparing sections which compare inputted address information and redundancy address information to be substituted to the auxiliary memory cells for every bit based on an EXCLUSIVE-OR control which is constituted of a combinational logic circuit, a logic composing section which performs a logic operation of output signals from the comparing sections by combinational logic circuits and judges the accordance/discordance of the address information and the redundancy address information, and an input setting section which supplies input signals of a predetermined logic level in place of respective bit signals of address information to at least one of the comparing sections, wherein based on a non-redundancy setting signal from the redundancy setting section which indicates that the absence of substitute is set, the input setting section is activated.
In a redundancy judging method of a semiconductor memory device according to another aspect of the present invention, in case presence of substitute to auxiliary memory cells is set with respect to memory cells of a predetermined address, inputted address information and redundancy address information to be substituted to the auxiliary memory cells are compared to each other for every bit based on an EXCLUSIVE-OR control which is constituted of combinational logic, and comparison results obtained by the comparison operation are subjected to a logic operation based on combinational logic and the accordance/discordance of the address information and the redundancy address information is judged thus performing the redundancy judgment whether the change to the auxiliary memory cells is to be executed or not, and in case absence of substitute is set, the address information is set to a predetermined value so that the redundancy judging result of absence of substitution to the auxiliary memory cells is obtained.
Accordingly, with respect to the redundancy judging unit such as the redundancy judging circuit or the redundancy judging method in which the redundancy judgment which judges the accordance judgment of the address information and the redundancy address information is performed such that the address information and the redundancy address information are subjected to the comparing operation for every bit by performing the EXCLUSIVE-OR control using the combinational logic circuit or other combinational logic and, thereafter, the comparison results are subjected to the logic operation using the combinational logic circuit or other combinational logic whereby the redundancy judgment can be performed in a static manner, when there is absence of substitute to the auxiliary memory cells due to the non-redundancy setting signal or the like and the redundancy judgment is unnecessary, the inputting of the address information to at least one comparing units such as comparing sections or comparing processes for each redundancy judging unit is interrupted. Then, at least one input setting units such as input setting sections, input setting processes or predetermined value supplying processes are activated so that predetermined values such as predetermined logic levels or the like are set in place of respective bit signals of address information.
Accordingly, due to respective bit signal of address information whose logic levels is fixed, the operation ranging from the operation of the comparing unit to operation of the logic composing unit in a subsequent stage such as logic composition section or the judging process of accordance/discordance are stopped for every redundancy judging unit so that the undesired current consumption can be reduced.
Here, in case the input setting units are provided to all comparing units, respective bit signals of address information are not connected to input loads of the comparing units and hence, an undesired driving current is not consumed with respect to the transition of the address information. Further, to obtain the comparison result of discordance, it is unnecessary to fix the inputs to all comparing units to a predetermined value such as a predetermined logic level or the like. That is, it is sufficient if at least one input setting unit is provided and the comparison result of discordance can be obtained with respect to at least one bit signal whereby the current consumption caused by the input setting unit can be reduced to the necessity of the minimum amount.
In a semiconductor memory device in which a plurality of auxiliary memory cells which are individually subjected to the substitute control for respective different redundancy judging unit are present, only redundancy judging unit which is subjected to the change setting can be operated so that the current consumption caused by the redundancy judging operation can be reduced to the necessity of the minimum amount.
Since individual comparing unit is also constituted of combinational logic circuit or the like, different from the dynamic-type constitution of the prior art, the input load of terminals to which respective bits of address information are inputted is small. The driving current for the input load caused along with the transition of the address information is also small whereby the current consumption reduction effect which is brought about by limiting the redundancy judging unit to be operated can be enhanced.
Further, with respect to the redundancy judging unit which is served for absence of substitution to the auxiliary memory cells, due to the input setting unit, the input of address information is interrupted and a predetermined logic level or the like is set in place of respective bit signal of address information and hence, the address information is not inputted to the comparing unit. Accordingly, even when the address information is changed, the comparing unit constituting the input stage of the redundancy judging unit which does not perform the redundancy judgment is not operated and hence, the undesired current consumption can be reduced.
In the DRAM or the like which is used in the portable equipment, it is possible to reduce the current consumption caused by the redundancy judging unit during the refreshing operation for reducing the standby current to a limit and hence, the continuous use time characteristics at the time of battery driving can be enhanced.
When the semiconductor memory device is provided with the refreshing redundancy function, the semiconductor memory device is provided with a larger number of redundancy judging units compared to the usual DRAM or the like. In this case also, the operation of the undesired redundancy judging units can be stopped and hence, in addition to the reduction of the current consumption caused at the time of performing the refreshing operation using the refreshing redundancy function, it is also possible to reduce the current consumption caused by the redundancy judgment. The current consumption during standby time can be also reduced so that the continuous use time characteristics at the time of battery driving can be further enhanced.
Further, along with the lowering of the use rate of the auxiliary memory cells caused by the progress of optimization of the manufacturing process, the frequency of redundancy judgment is reduced so that the number of the undesired redundancy judging units are increased. Since the operations of these redundancy judging units can be individually stopped, it is possible to effectively reduce the current consumption of the semiconductor memory device in response to the use rate of the auxiliary memory cells.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in conjunction with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of the illustration only and are not intended as a definition of the limits of the invention.